Microblaze [ PART1 ]

: Presentation
: eCos HAL
: Virtex5 Target board
: Footprint / Dhrystone Benchmark
: Creating external IPs

I. Literature

- Xilinx Microblaze processor reference guide (EDK 12.3)
- Xilinx Embedded System Tools Reference manual (EDK 12.3)

II. Purpose

The purpose of this section is to develop an eCos HAL for the Xilinx Microblaze soft core. The port shall support a set of basic peripherals. The debug channel and/or UART is developed around the XPS UART Lite. The RTC clock make use of the XPS Timer IP block. To allow for multiple external interrupt sources, the block XPS Interrupt Controller is required. Additionaly, an Ethernet driver for the TriMode Ethernet MAC will be part of the port. Complete list of IP blocks available from Xilinx here.

In typical design, the microblaze uses 2 interconnection buses to attached peripherals to itself. The LMB (Local Memory Bus) and PLB (Processor Local Bus). The former is typically used to access internal block RAM that can be used for storing both instruction and data. The later allows the core to access Xilinx peripherals such as Timers, UART, memory controller etc. Other bus such as the FSL (Fast Simplex Link) can be used to attached hardware co-processor designed to fit the user needs (typical examples are encryption, FFT etc.). Large application may require external memory (volatile or non-volatile) while other application may run without it. Internal BRAM can expend up to 1MB on certain Xilinx devices which is more than enough to run eCos default template with the lwip stack. While being volatile memory, the BRAM can store redboot or other type of boot loader, the BRAM memory content is part of the FPGA bit stream. The microblaze core is fully configurable. The default template gives priority to smaller footprint over functionality. The core can be customized at any point during the design phase. Instruction and data cache can be added up to 32KB large, FPU can be enable, exception handling is also disabled in the default template. Other core feature includes barrel shifter, integer multiplier/divider, pattern comparator. The core default executes its first instruction from address 0x0 but with data and instruction cache enable at startup, it is possible to boot from external memory to remove the need of LMB memory.

III. Generate soft core - Xilinx EDK

To build the Xilinx microblaze soft core, the Xilinx Embedded Development Kit (EDK) is required. The software allows to generate and customize the processor in a few steps:

01. Open Xilinx Platform Studio and create a new project with the BSD wizard.

IV. Configuring Microblaze core

The microblaze core is fully configurable from EDK by right clicking on the peripheral and selecting -> configure IP

01. The microblaze configuration wizard includes some default templates optimized for diverse criteria (speed, area, Linux OS etc..).

V. Debugging the software

To debug the software running on microblaze core, it is possible to use the Xilinx parallel cable. It exists an USB version as well. In contrary to other JTAG debuggers like BDI, Zylin Probe etc., the Xilinx probe does not integrate a GDB server. Instead, the GDB server is integrated in the Xilinx® Microprocessor Debugger (XMD) engine. The Xilinx XMD engine translate the GDB commands to JTAG commands.

The Xilinx XMD engine can be started from the EDK tool, from Debug->Launch XMD... In order to use the JTAG interface, the target board must be prepared for it. The following schematic extracted from Xilinx ug360.pdf showns the connection between the JTAG connector and the FPGA.

It is recommended to have the FPGA mode pins in JTAG configuration mode, M2 = 1, M1 = 0 and M0 = 1.

VI. U-Boot / Linux

- Xilinx wiki for compiling U-boot.
- Xilinx wiki for compiling Linux.