Microblaze [ PART4 ]

: Presentation
: eCos HAL
: Virtex5 Target board
: Footprint / Dhrystone Benchmark
: Creating external IPs

I. HAL footprint

The eCos minimal HAL + kernel is compiled and compare for different atchitectures (Microblaze, ARM7, PowerPC E500 and Cortex-M3). Compilation is done with level 2 of optimization (O2). The application remains the same, a single task including a forever loop with a diag_printf call. Microblaze HAL footprint is almost 170% larger than the Cortex-M3 HAL. (Cortex-M3=15KB, ARM7=17KB, PPC=19KB and Microblaze=25KB).





Test is carried out with FPU disable. Footprint is measured as the text section only. GCC 4.5 is used for the ARM7, PPC and Cortex-M3 architecture. GCC 4.6 is used for the Microblaze architecture. List of packages included in the test:

CYGPKG_HAL_Arch
CYGPKG_HAL_Variant
CYGPKG_HAL_Platform
CYGPKG_HAL
CYGPKG_IO
CYGPKG_INFRA
CYGPKG_ERROR
CYGPKG_ISOINFRA
CYGPKG_KERNEL

For any application that relies on the eCos kernel, at least 64KB or more memory is required which means either a large Spartan device, a smaller Virtex part or the use of external RAM. For products that are FPGA centric, it is anyway required to use an external FLASH to load the FPGA bit stream. The FLASH can also be used to store the application code which can be rellocated to external RAM at run time.


II. Dhrystone Benchmark

Target Result
Spartan3AN - 62.5MHz Caches OFF
Spartan3AN - 62.5MHz Caches ON